A System on Chip (SOC) is an integrated circuit in which all components of an electronic system, such as a computer system, are integrated on a single semiconductor die. For example, an SOC may include one or more processors, RAM, and input/out (I/O) interfaces for off-chip communication. Some SOCs may further include programmable logic and routing resources such as those found in field programmable gate arrays (FPGAs).
The major components, which are referred to herein as “circuit blocks,” of an SOC may operate at different clock speeds. For example, the processor, memory, and I/O interfaces may be rated to operate at different frequencies. There may be twenty or more circuit blocks on some SOCs, with each circuit block requiring a different clock speed.
In some SOCs, the clock signal from an oscillator and a master phase locked loop (PLL) is delivered to the circuit blocks through a clock network having programmable frequency dividers. A programmable frequency multiplier may be configured to boost the oscillator frequency to a rate greater than or equal to the greatest frequency required by one of the circuit blocks, and the frequency dividers may be configured to reduce the boosted frequency to rates required by the circuit blocks.
Determining a suitable set of values for configuring the frequency multiplier and the frequency dividers may be problematic, because there may be a large number of circuit blocks and numerous possible combinations of configuration values for the frequency multiplier and frequency dividers. The combination of configuration values for the frequency multiplier and frequency dividers may be referred to herein as a “solution set.”
A prior approach selected a solution set having the least overall error rate, where the error rate is the sum of the absolute differences between the required frequencies of the circuit blocks and the actual frequencies that would be provided to the circuit blocks using the selected values for the frequency multiplier and dividers. However, a particular solution set may not be feasible in some instances, even though the overall error rate of the solution set may be less than the overall error rate of an alternative solution set. A solution set is not feasible if the configuration values for the frequency multiplier and frequency divider for any one of the circuit blocks would produce a frequency that is unsuitable for that circuit block. In this scenario, a designer may be faced with having to manually determine a suitable solution set, assuming a feasible solution set even exists, or choose another solution set that may be less desirable than some other solution set.